In the manufacturing of semiconductor devices, stress may change the band gap and the carrier mobility of the silicon material, thus improving the performance of the MOS transistors by the stress has become a more and more common method. Carriers in the NMOS transistors are electrons; and carriers in the PMOS transistors are holes. Specifically, by properly controlling the stress in the cannel region, the carrier mobility of the CMOS transistors can be increased, thus the drive current of the CMOS transistors can be increased; and the performance of the CMOS transistor may be significantly improved.
The embedded SiGe technology can be used to generate a compressive stress to the channel region of a PMOS transistor, so as to increase the carrier mobility of the holes. That is, SiGe structures are formed in the regions for subsequently forming source/drain regions firstly; then the SiGe structures are doped to form the source/drain regions. The SiGe structures and the substrate of the PMOS transistors may have a lattice mismatch, thus a compressive stress may be generated in the channel region of the PMOS transistor; and the performance of the PMOS transistor may be improved.
FIGS. 1˜11 illustrate semiconductor structures corresponding to certain stages of an existing fabrication process of CMOS transistors.
As shown in FIG. 1, at the beginning of the fabrication process, a semiconductor substrate 100 is provided. The semiconductor substrate 100 includes at least one first region 11 and at least one second region 12. The first region 11 is used to form a PMOS transistor; and the second region 12 is used to form an NMOS transistor. A poly silicon layer (not shown) is formed on the semiconductor substrate 100. A patterned mask layer 103 made of the silicon nitride is formed on the poly silicon layer; a first gate 101 is formed on the semiconductor substrate 100 in the first region 11; and a second gate 102 is formed on the semiconductor substrate 100 in the second region 12 by etching the semiconductor substrate 100 using the pattered mask 103 as an etching mask. Then, a thermal oxide layer (not shown) is formed on surfaces of the first gate 101, the second gate 102 and the semiconductor substrate 100 by a thermal oxidation process.
As shown in FIG. 2, after forming the first gate 101 and the second gate 102, sidewall spacers 104 made of silicon nitride are formed on the side surfaces of the first gate 101 and the second gate 102. Further, first lightly doped regions 105 are formed in the surface of the semiconductor substrate 100 in the first region 11 at both sides of the first gate 101 by a P-type ion implantation process using the mask layer 103, the first gate 101 and the first sidewall spacers 104 as a mask. The doping concentration of the lightly doped region is smaller than the doping concentration of the subsequently formed heavily doped region.
As shown in FIG. 3, after forming the first lightly doped regions 105, a second sidewall spacer material layer 106 made of silicon oxide is formed to cover the semiconductor substrate 100, the patterned mask layer 103 and the first sidewall spacers 104. Further, a third sidewall spacer material layer 107 made of silicon nitride is formed on the second sidewall spacer material layer 106. Further, a photoresist mask 108 is formed to cover the third sidewall spacer material layer 107 in the second region 12.
As shown in FIG. 4, after forming the photoresist mask 108, second sidewall spacers 109 are formed on the side surface of the first gate 101; and the third sidewall spacers 110 are formed on the second sidewall spacers 109 by etching the third sidewall spacer material layer 107 and the second sidewall spacer material layer 106 in the first region 11. The second sidewall spacers 109 are used as stop layers for subsequently removing the third sidewall spacers 110. The third sidewall spacer material layer 107 and the second sidewall spacer material layer 106 are kept for subsequently selectively forming a SiGe source region and a SiGe drain region in the first region 11.
As shown FIG. 5, after forming the second sidewalls 109 and the third sidewall spacers 110, the photoresist mask 108 is removed; and the trenches 111 are formed in the semiconductor substrate 100 at both sides of the third sidewall spacers 109 in the first region 11. The trenches 111 are formed by etching the semiconductor substrate using the patterned mask layer 103, the first sidewall spacer 104, the second sidewall spacers 109 and the third sidewall spacers 110 as an etching mask. The trenches 111 are rectangular.
After forming the trenches 111, a wet cleaning process is used to clean side surfaces and bottom surfaces of the trenches 111 to remove oxide layers on the side surfaces and the bottom surfaces of the trenches 111. After the wet cleaning process, the side surfaces and the bottom surfaces of the trenches 111 would keep a relatively high cleanliness; and the relatively high cleanliness helps subsequently formed sigma shape trenches to have a desired geometry.
The cleaning solution of the wet cleaning process is a hydrogen fluoride (HF) solution. Because the second sidewall spacers 109 are made of silicon oxide, when the trenches 111 is being cleaned by the HF solution, as shown in FIG. 6, the second sidewall spacers 109 at the bottom of the third sidewall spacers 110 are also etched simultaneously; and lateral shrinking defects 13 are formed. Because the number of the first gate 101 formed on the semiconductor substrate 100 is a plural, after forming the second sidewall spacers 109 on the side surfaces of a plurality of first gates 101, the thickness differences of the second sidewall spacers 109 on both sides of each of the first gate 101 and/or on both sides of the first gates 101 at different regions may exist because of limitations or differences of the etching processes. After cleaning the trenches 111 with the wet cleaning process, because of the thickness differences of the second sidewall spacers 109 and the limitations of the etching processes, the shrinkages of the lateral shrinking defects 13 of the second sidewall spacers 109 on the side surfaces of a same first gate 101 may be different; shrinkages of the lateral shrinking defects 13 of the second sidewall spacers 109 on side surfaces of the different first gates 101 may also be different.
As shown in FIG. 7, after cleaning the trenches 111, sigma-shape trenches 112 are formed by etching the trenches 111. The sigma-shape trenches 112 have apex angles directing to the channel region of the PMOS transistor. The trenches 111 are etched by a TMAH solution to form the sigma-shape trenches 112. Because of the shrinking defects 13, the etching starting positions of the sigma-shape trenches 112 may change. Referring to FIG. 7, deviations between the positions of the apex angles of the sigma-shape trenches 112 and positions of apex angles of designed sigma-shape trenches (illustrated with dashed lines in FIG. 7) are formed. Such deviations may deteriorate the control of the electrical stability of the PMOS transistor. Further, because of the shrinkage differences of the shrinking defects 13, corresponding positions of the apex angles of the sigma-shape trenches 112 are different, the uniformity of the apex angles of the sigma-shape trenches 112 may be not acceptable; and the uniformity of the electrical properties of subsequently formed transistors may also not acceptable neither.
As shown in FIG. 8, after forming sigma-shape trenches 112, the sigma-shape trenches 112 are filled up with SiGe, and SiGe source/drain regions 113 are formed. The SiGe source/drain regions 113 are formed by a selective epitaxial process.
As shown in FIG. 9, after forming the SiGe source/drain regions 113, second sidewall spacers 109 are formed on the first sidewall spacers 104 on the second gate 102 in the second region 12. Further, third sidewall spacers 110 are formed on the second sidewall spacers 109. The second sidewall spacers 109 and the third sidewall spacers 110 on the second gate 102 in the second region 12 of the semiconductor substrate 100 are formed by etching the third sidewall spacer material layer 107 and the second sidewall spacer material layer 106 on the second gate 102 in the second region 12 by a mask-less etching process (an etch back process).
Referring to FIG. 9, after the mask-less etching process, a portion of the second sidewall spacer material layer 106 and a portion of the third sidewall spacer material layer 107 on the top of the patterned mask 103 are removed. Thus, when the third sidewall spacers 110 are subsequently removed, the patterned mask 103 in the second will be removed simultaneously. The mask-less etching process generates some damages to the semiconductor substrate 100.
As shown in FIG. 10, after forming the second sidewall spacers 109 and the third sidewall spacers 110 in the second region 12, the third sidewall spacers 110 and the patterned mask layer 103 are removed by a wet etching process. Because the third sidewall spacers 110 are already damaged by previous processes, it may be difficult to control positions of subsequently formed heavily doped regions, the third sidewall spacers 110 need to be removed before forming the heavily doped regions. Further, the second sidewall spacers 109 are used for forming second lightly doped regions 114 in the semiconductor substrate 100 in the second region 12. Specifically, an N-type ion implantation process is performed onto the semiconductor substrate 100 at both sides of the second sidewall spacer 109 in the second region 12 using the second sidewall spacers 109, the first sidewall spacers 104 and the second gate 102 in the second region 12 as a mask; thus the second lightly doped regions 114 are formed.
As shown in FIG. 11, after removing the third sidewall spacers 110 and the patterned mask 103, the fourth sidewall spacers 115 are formed on the second sidewall spacers 109 in the first region 11 and the second region 12. Further, third heavily doped regions (not shown) are formed in the semiconductor substrate 100 in the first region 11 at both sides of the first gate 101 by a P-type ion implantation process using the fourth sidewall spacers 115 and the first gate 101 in the first region 11 as a mask. The third heavily doped regions can also be formed by an epitaxial process with an in situ doping. The first lightly doped regions 105 and the third heavily doped region together form the source/drain regions of a PMOS transistor. Further, fourth lightly doped regions (not labeled) are formed in the semiconductor substrate 100 in the second region 12 at both sides of the second gate 102 by an N-type ion implantation process using the fourth sidewall spacers 115 and the second gate 102 in the second region 12 as a mask. The second lightly doped regions 114 and the fourth heavily doped regions together form the source/drain regions of the NMOS transistor.
Because the uniformity of the apex angles of the sigma-shape trenches 112 may be not acceptable, the uniformity of the electrical properties of subsequently formed transistors may also not acceptable neither. The disclosed device structures and methods are directed to solve the un-uniformity issues of the apex angles of the sigma-shape trenches during forming CMOS transistors with the embedded SiGe technology set forth above; and other problems.